View AN2857_8357759.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

august 2011 doc id 15241 rev 3 1/31 AN2857 application note stm8s and stm8a family power management introduction this application note is intended for system designers who require a hardware implementation overview of the low-power modes of the stm8s and stm8a product families. it shows how to use the stm8s an d stm8a devices in these modes, describes how to take power consumption and wakeup time measurements, and gives results for such measurements. example firmware is provided with this application note for implementing and measuring the consumption and wakeup time of the different stm8s and stm8a functioning modes. www.st.com
contents AN2857 2/31 doc id 15241 rev 3 contents 1 power consumption factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 internal supply structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 io supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 clock system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 clock configuration and power management . . . . . . . . . . . . . . . . . . . . . . 11 4 run and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.1 entering wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.2 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.3 activation level/low-power mode control . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.1 entering active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.2 exiting active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.3 voltage regulator and flash configuration during halt phase . . . . . . . . . 16 4.3.4 awu unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4.1 entering halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4.2 exiting halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4.3 flash configuration during halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 power consumption and wakeup time measurement s and results . . 18 5.1 power consumption measurements and results . . . . . . . . . . . . . . . . . . . . 18 5.1.1 measurement configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 power consumption results in run mode . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 power consumption results in wait mode . . . . . . . . . . . . . . . . . . . . . . . . 22
AN2857 contents doc id 15241 rev 3 3/31 5.1.4 power consumption results in active halt mode . . . . . . . . . . . . . . . . . . . 23 5.1.5 power consumption results in halt mode . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.6 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 wakeup time measurements and results . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 measurement configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 wakeup time results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 wakeup time results in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.4 wakeup time results in active halt mode . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.5 wakeup time results in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.6 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 power management tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 rules to help minimize power consumption . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 choosing the optimal low-power mode for an application . . . . . . . . . . . . 29 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of tables AN2857 4/31 doc id 15241 rev 3 list of tables table 1. clock source comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. clock selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. functioning modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. active halt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. power consumption results in run mode, code executed from flash . . . . . . . . . . . . . . . . . 21 table 6. power consumption results in run mode, code executed from ram . . . . . . . . . . . . . . . . . 21 table 7. power consumption results in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. power consumption results in active halt mode (mvr on lpvr off) . . . . . . . . . . . . . . . . . 23 table 9. power consumption results in active halt mode (mvr off lpvr on) . . . . . . . . . . . . . . . . . 23 table 10. power consumption results in halt mode (mvr off lpvr on) . . . . . . . . . . . . . . . . . . . . . . 23 table 11. wakeup time results in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. wakeup time results in active halt mode (mvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. wakeup time results in active halt mode (lpvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. wakeup time results in halt mode (lpvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AN2857 list of figures doc id 15241 rev 3 5/31 list of figures figure 1. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. active halt diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. power supply setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. crystal oscillator setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. wakeup time measurement diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
power consumption factors AN2857 6/31 doc id 15241 rev 3 1 power consumption factors in complementary metal oxide semiconductor (cmos) digital logic devices, power consumption is a sum of: static power (caused mainly by transistor polarization and leakage) dynamic power which depends on the supply voltage and the clock frequency through the formula: dynamic power = c v 2 f, where: ? c is the cmos load capacitance ? v is the supply voltage ? f is the clock frequency. static consumption is negligible compared to dynamic consumption when the clock is running. in some low-power modes, when no clock is running, static consumption is the main consumption source. power consumption thus depends on: microcontroller unit (mcu) chip size: technology used, number of transistors, analog features/peripherals embedded and used. mcu supply voltage : the amount of current used in cmos logic is directly proportional to the voltage of the power supply squared . thus, power consumption may be reduced by lowering the mcu supply voltage. clock frequency : power consumption may be reduced by decreasing the clock frequency when fast processing is not required by the application. number of active peripherals or mcu features used (css, bor, pvd,...): the greater the number of active peripherals or features, the greater the power consumed. operating mode : power consumption varies depending on the mode a particular application is running in (cpu on/off, oscillator on/off,...). for an application powered by a battery, consumption is very important. usually, average consumption should be below a certain target to ensure an optimum battery lifetime. this means that an application can consume more for short periods of time and keep its average current consumption below the target.
AN2857 power supply doc id 15241 rev 3 7/31 2 power supply 2.1 internal supply structure stm8s and stm8a devices require a 3 v to 5.5 v operating voltage supply (v dd ). two embedded regulators, the main voltage regulator (mvr) and the low-power voltage regulator (lpvr), are used to provide 1.8 v supply to the internal digital parts, depending on the functioning mode (see figure 1 ). the v cap pin is used to decouple the internal 1.8 v supply. a capacitor of minimum 470 nf has to be connected between this pin and the ground. the 1.8 v should never be provided by an external voltage regulator through this pin. refer to the stm8s and stm8a reference manual (rm0016) which is available on st.com for more details. figure 1. power supply overview 2.2 analog supply the analog-to-digital converter (adc) of stm8s and stm8a devices is powered by an independent power supply. the digital and analog power supply have to be properly decoupled. refer to the stm8s and stm8a reference manual for more details about decoupling capacitors. 2.3 io supply the ios have dedicated pins for power supply which have to be properly decoupled with recommended capacitors. refer to the stm8s and stm8a reference manual for more details about decoupling capacitors. adc main voltage regulator (mvr) low-power voltage regulator (lpvr) i/o buffers mcu core cpu ram flash v cap v dd v ddio 3 v 5 v 3 v 5 v 1.8 v v dda v ssa ai15044
power supply AN2857 8/31 doc id 15241 rev 3 2.4 voltage regulator after reset, the mvr provides the 1.8 v to the internal digital parts of the microcontroller. depending on the functioning mode, the mvr can be switched off at which time the lpvr provides the 1.8 v. for example: in run and wait mode, only the mvr provides the 1.8 v. the lpvr cannot be used in run mode. in active halt mode, during the halt phase, either the mvr or the lpvr can provide the 1.8 v. the user can select which regulator to be used. in halt mode, the lpvr is automatically used. the mvr cannot be used in halt mode.
AN2857 clock management doc id 15241 rev 3 9/31 3 clock management 3.1 clock system overview four different clock sources can be used to drive the master clock: 1-24 mhz high speed exte rnal clock from the crystal oscillator (hse crystal) up to 24 mhz high speed external clock provided by the user (hse user-external) 16 mhz high speed internal rc oscillator (hsi) 128 khz low speed internal rc oscillator (lsi) each peripheral clock source can be switched on or off independently when it is not used, to optimize power consumption. this is done by using the peripheral clock gating (pcg) feature. see the ?clock control? sections of the stm8s and stm8a reference manual for more details. ta bl e 1 summarizes the main features of each clock source. stm8s and stm8a devices offer a complete range of clock sources to fit customer application requirements in terms of cost, accuracy and consumption. 1. factory calibrated by stmicroelectronics at t a = 25 c. table 1. clock source comparison hse crystal hse external hsi lsi cost low to medium free to high free free accuracy crystal external source 1 % (1) 2.5 % (1) consumption (1) high medium low very low other information resonator or crystal existing clock to very complex clock systems --
clock management AN2857 10/31 doc id 15241 rev 3 figure 2. clock tree the read-only clk_cmsr register contains th e current selection of master clock sources (for core and peripherals). selection of the ?next? master clock is made through the writable clk_swr register, the content of which is copied into the clk_cmsr register once the change is effective (see details below). refer to ta bl e 2 for clock selection values. hse osc 1 - 24 mhz hse ext oscout css oscin extclk option bit his rc 16 mhz lsi rc 128 khz hsidiv[1:0] /8 / 4 / 2 / 1 master clock switch /1 /2 /4 /8 /16 /32 /64 /128 ckm[7:0] cpudiv[2:0] f master f cpu f hse f hsi f hsidiv f lsi peripheral clock enable (11 bits) to peripherals to cpu and window watchdog to auto wakeup and independent watchdog prescaler prsc[1:0] option bits ckawusel option bit /1, /2, ../8 candiv[2:0] to becan f hsi f hsidiv f hse f lsi f master f cpu f cpu/2 f cpu/4 f cpu/8 f cpu/16 f cpu/32 f cpu/64 ccosel[3:0] cco configurable clock output ai15045
AN2857 clock management doc id 15241 rev 3 11/31 the default clock after reset is hsi/8. the user can then switch the clock to different frequencies and sources by: choosing another prescaler (/1, /2, /4 or /8) for an internal rc 16 mhz (hsi) clock through the hsidiv[1:0] bits in the clk_ckdivr register. changing the clock master (to hse or lsi ). refer to the stm8s and stm8a reference manual for more details about the clock switching mechanism. before switching off a previous clock source when using automatic switching mode, the user must ensure that the core is no longer running on the current clock. this means that the previous clock must be turned off after the swif flag has been set. if the user tries to switch off the clock and the swif flag has not been set by hardware, the current clock is not switched off as the microcontr oller is still running on it. such clock switching can be combined with wait mode (for example, if the hse crystal is the new clock) as clock switch execution interrupt can wake up the mcu from wait mode. this allows the mcu wakeup to be synchron ized with the new clock availability. the clock switching feature can also be used at the beginning and end of a regular or interrupt routine to speed it up (for instance, if the clock master is lsi rc, but, some parts of the code have to be executed quickly with hsi rc). note: when the device is running on an external clock with a frequency above 16 mhz, the wait state bit in the option bytes has to be set. this adds a wait state to the flash memory access. 3.2 clock configuration and power management in addition to the flexibility of the cloc k sources, different complementary clock configurations and features are available to optimize power consumption of the device: pcg: each peripheral clock can be switched off through the clk_pckenrx registers. cpu clock divider from 1 to 128 (cpudiv[0:2] bits from the clk_ckdivr register): the cpu frequency can be decreased and not the frequency of the peripherals. table 2. clock selection table register value clock master source (clk_cmsr) next clock master (clk_swr) e1h hsi hsi d2h lsi lsi b4h hse hse other reset current clock master kept
run and low-power modes AN2857 12/31 doc id 15241 rev 3 4 run and low-power modes by default, after a reset, the microcontroller is in run mode. the default cpu clock is a 16 mhz hsi divided by eight due to the hsidiv register reset value. several low-power modes are available to save power when it is not needed to keep the cpu running, for example, when waiting for an external event. it is up to the user to select the mode that gives the best compromise between low power consumption, short startup time, good peripheral functionality, and availability of wakeup sources. stm8s and stm8a devices feature three main low-power modes: wait mode (cpu stopped, peripherals kept running) active halt mode (cpu stopped, awu (auto wakeup) and iwdg (independent watchdog) kept running if activated). halt mode (everything is stopped) power consumption in run and wait mode can also be reduced by one of the following means: slowing down the system clocks gating the clocks to the peripherals when they are not used ta bl e 3 summarizes the functioning modes of stm8s and stm8a devices. it gives an overview of the mode combinations which can be used to fit an application?s requirements in terms of consumption and wakeup time. note: when the lpvr is used, the mvr is automatically switched off. table 3. functioning modes mode voltag e regulator flash oscillators cpu peripherals entry wake up trigger event run mvr on on on on - - wait mvr on on off on execute wfi (1) instruction 1. wfi = wait for interrupt all internal or external interrupts and reset active halt mvr on off except lsi or hse off awu and iwdg on (if activated) enable the awu then execute halt instruction awu or external interrupts and reset off lpvr on off except lsi or hse off halt lpvr on off off off execute halt instruction external interrupts and reset off
AN2857 run and low-power modes doc id 15241 rev 3 13/31 4.1 run mode run mode is the default functioning mode of stm8s and stm8a devices. this mode is used for normal operations and consumes the most power. use of pcg and low speed clock sources reduce power consumption of the device in run mode. clock frequency can be slowed down in several ways. for example, the lsi clock can be used as the f master clock. to enable the mcu to run on the lsi clock, the lsi_en option bit must be set. refer to the stm8s and stm8a datasheets (which are available on st.com) for more details about the option byte configurations. 4.2 wait mode wait mode, or more exactly wait for interrupt mode, is designed to reduce stm8s and stm8a device power consumption by switching off the core when it is not used. wait mode is mainly used when the stm8s or stm8a device is waiting for an external or internal event which allows the program to continue its execution. instead of waiting for the event in run mode, the device can be switched to wait mode. this mode can be used with pcg and with a low speed clock source to further reduce power consumption of the device. 4.2.1 entering wait mode wait mode is entered by executing the wfi assembly instruction. this stops the cpu, but, allows other peripherals and the interrupt controller to continue to run. when entering wait mode, the interrupts are automatically enabled. 4.2.2 exiting wait mode when an internal or external interrupt request occurs, the cpu wakes up from wait mode and resumes processing. this mode offers the lowest wakeup time. examples of peripherals or feat ures with interrupts having ex it-from-wait ca pability include: i 2 c usart spi can adc awu external interrupt timers clock controller (clock switch execution) refer to the stm8s and stm8a reference manual for more details on the functioning of the above peripherals and features . refer to the stm8s and stm8 a datasheets fo r availability of above peripherals and features on particular devices.
run and low-power modes AN2857 14/31 doc id 15241 rev 3 4.2.3 activation level/ low-power mode control in a very low-power application, the mcu spends most of the time in wfi/halt mode and is woken up (through interrupts) at specific moments to execute particular tasks. some of these tasks are recurring and short enough to be treated directly in an interrupt service routine (isr), rather than returning to the main program. in this case, setting the al bit before going to wait mode, ensures the run time/isr execution is reduced because the ?context? (core register content) is not saved/restored each time. in very simple applications, all operations can be executed in isr only. in more complex applications, an interrupt routine may relaunch the main program by resetting the al bit. the activation level/low-power mode control feature works only with wait mode. it is not available for active halt or halt mode. 4.3 active halt mode active halt mode can be defined as a ?hybrid? mode between run and halt mode. it is composed of two phases: halt phase: in this phase, the mcu is in halt mode except that the awu unit and the lsi clock are kept running if they are used as the awu clock source. active phase: in this phase, the mcu is in run mode. when entering active halt mode, the awu counters start to run. the awu interrupt wakes up the cpu at regular programmed intervals. once the device is in run mode the awu counters are stopped. figure 3. active halt diagram in active halt mode during halt phase, the user can choose the regulator (either mvr or lpvr) and the flash state (either operating or power-down mode). using the lpvr and putting the flash in power-down mode reduces power consumption, but, increases wakeup time. active halt mode is very useful for reducing average consumption of a battery based application. run halt phase awu time interval awu interrupt mcu state run go to halt mode ai15046
AN2857 run and low-power modes doc id 15241 rev 3 15/31 4.3.1 entering active halt mode to enter active halt mode, configure and enable the awu. then execute the halt instruction. note: if the iwdg is enabled before the halt instruction is executed, the device does not switch to halt mode, but, switches to the halt phase of active halt mode. in this case, if the awu is not enabled, the mcu does not wake up automatically. the mcu wakes up by an iwdg reset or external reset. 4.3.2 exiting active halt mode each time an awu event occurs, the mcu goes into run mode. so, the awu is used as a wakeup source. however, during active halt mode, the mcu can be woken up by any halt mode wakeup source (see section 4.4: halt mode for more details about wake-up sources). fast clock wakeup a fast wakeup time is very important in active halt mode. it supplements the effect of the cpu processing performance by helping to minimize the time the mcu stays in run mode between two periods in low-power mode. fast wakeup time thus reduces overall average power consumption. after a wakeup event, device startup is on the clock selected before entering active halt mode. the longest wakeup time is obtained when the clock is an hse crystal. this is mainly due to the oscillator stabilization time. to reduce this wakeup time, stm8s and stm8a devices offer a feature called ?fast clock wakeup? which allows the device to start automatically on an hsi clock after a wakeup event. the user can decide to switch back to the former clock or stay on the hsi clock. by default, the fast clock wakeup feature is disabled. to enable it, the fhwu bit of the internal clock register (clk_ickr) must be set before entering low-power mode. table 4. active halt mode configuration voltage regulator flash state power consumption (1) 1. the greater the number of stars, the great er the power consumption or the wakeup time. wakeup time (1) mvr on **** * off *** ** lpvr on ** *** off * ****
run and low-power modes AN2857 16/31 doc id 15241 rev 3 4.3.3 voltage regulator and fl ash configuration during halt phase when entering active halt mode, the mvr is the default voltage regulator and the flash is in operating mode. to use the lpvr, the swuah bit of the internal clock register (clk_ickr) has to be set. to put the flash in power-down mode, the ahalt bit of flash control register 1 (flash_cr1) must be set. 4.3.4 awu unit the awu unit is the heart of active halt mode. it generates regular time-spaced interrupts used for waking up the mcu from halt mode. two clock sources can feed the awu: lsi clock hse crystal divided by a prescaler (presc) and selected by the option bytes to give an input clock of about 128 khz. the awu counters only run in halt phase of active halt mode. once a wakeup event occurs, the device wakes up and the counters are stopped. it is impossible to keep the awu counters running in run mode. when the device enters halt phase again, the counters restart from zero. the awu delivers regular time-spaced interrupts in the range 15.625 s to 30.720 s (for an awu input clock of about 128 khz). the average power consumption of the device (i tot ) in active halt mode can be estimated using equation 1 . equation 1 t awu is the duration of halt phase of active halt mode. it is the time base of the awu. i run is the consumption in run mode which depends on many factors. good approximations of this parameter are given in ta bl e 5 and ta bl e 6 . i ahalt is the consumption of halt phase of active halt mode. values given in ta b l e 8 , ta b l e 9 , and ta b l e 1 0 can be used. t run is the time the mcu spends in run phase between two halt phases. this time can be calculated using equation 2 . i tot t run t run ? t awu + () i run [] t awu t run ? t awu + () i ahalt [] + =
AN2857 run and low-power modes doc id 15241 rev 3 17/31 equation 2 t wkup is the time spent waking up the microcontroller and executing the first instruction of the interrupt routine. it depends on the halt phase configuration (regulator used and flash state). some typical values for this parameter are given in ta b l e 1 1 , ta b l e 1 2 , ta bl e 1 3 , and ta bl e 1 4 . t code is the execution time of the user routine. this time depends on the user code implementation. t shdw is the time taken for entering low-power mode. it depends on the halt phase configuration (regulator used and flash state). this time includes the context saving. 4.4 halt mode in halt mode, all clocks are stopped while the ram content and all registers are preserved. in this mode, the mvr regulator is switched o ff to limit power consumption. only the lpvr regulator is active. 4.4.1 entering halt mode the mcu enters halt mode when t he halt instruction is executed. 4.4.2 exiting halt mode wakeup from halt mode is triggered by an external interrupt, sourced by a gpio pin configured as an interrupt input or a peripheral interrupt. interrupts which can wake up the device from halt mode include: external interrupt (gpio) can receive interrupt spi end of transfer i 2 c interrupt (slave address match) reset 4.4.3 flash configur ation during halt mode by default, when entering halt mode, the flash is in power-down mode. to maintain the flash in operating mode during halt mode the halt bit of flash control register 1 (flash_cr1) must be set. when the flash is in power-down mode, the power consumption of the device is reduced but the wakeup time increases. t run t wkup t code t shdw ++ =
power consumption and wakeup time measurements and results AN2857 18/31 doc id 15241 rev 3 5 power consumption and wakeup time measurements and results the following measurements and results aim to highlight the impact of different low-power modes on mcu consumption and wakeup time. power consumptions given are typical values measured at 25 c. they are for guidance only. a zip file containing the software used to take these measurements is attached to this application note. refer to the electrical char acteristics sections of the stm8s and stm8a datasheets for real specifications. 5.1 power consumption measurements and results power consumption measurements are taken in run mode and low power modes. results are given in ta b l e 5 to ta bl e 1 0 . 5.1.1 measurement configuration v dda , v ddio1 , v ddio2 , and v dd are connected together to v dd v ssa , v ssio1 , v ssio2 , and v ss are connected together to v ss all ports are set as output low level (singl e wire interface module, swim, is disabled). all peripherals are disabled (even if enabled by default) if possible, all peripheral clocks are stopped (see the clk_pckenrx definition in the stm8s and stm8a reference manual). once the device is configured, the mcu is then put into the different functioning modes described in section 4: run and low-power modes . measurements are performed on an stm8s208mbt6 in an lqfp80 package. this is the ?super set? of the family which has the highest consumption rates. hardware environment run and low-power modes power consumption are measured simultaneously on v dd , v ddio and v dda . the hardware configuration is given in figure 4 : i tot = i vddio + i vdd + i vdda .
AN2857 power consumption and wakeup time measurements and results doc id 15241 rev 3 19/31 figure 4. power supply setup figure 4 does not show the decoupling capacitors for all power supplies. ceramic decoupling capacitors, with very low parasitc serial resistance, are used for the power measurements. current leakage through such decoupling capacitors is not visible. when the power measurements are performed with an external crystal, there is no internal clock division. the crystal is physically changed for each frequency. figure 5 shows the crystal oscillator setup. figure 5. crystal oscillator setup when the power measurements are taken with an external clock, the following configuration is used: the function generator provides a ?sin? waveform at a given frequency. the wave oscillates from 0 v to 5 v or 3.3 v depending on the supply vo ltage. as the oscout pin is not used, it is configured like other gpios (output push-pull outputting low level). stm8 a v ddio v dda v ssio v ssa v ss v dd 3.3 v or 5 v ai15047 stm8 oscin oscout c l1 = 22 pf c l2 = 22 pf ai15048
power consumption and wakeup time measurements and results AN2857 20/31 doc id 15241 rev 3 figure 6. external clock setup selection between the external clock and the cryst al oscillator is made by the external clock selection (extclk) option bit. refer to the option byte sections of the stm8s and stm8a datasheets for more details. firmware description for run mode measurements power consumption in run mode depends on several factors which are linked more to the application than to the mode itself. therefore, it is difficult to give some typical values. for example, consumption in run mode depends on the code executed and the code placement in the memory (the latter because of the pipeline and prefetch buffer). section 5.1.2: power consumption results in run mode gives an overview of consumption in run mode with the code executed from flash and ram memory. the code starts with the mcu configuration (gpio, pcg, ...). the mcu then enters an endless loop, executing a sequence of various instructions one hundred times. this is to benefit from the prefetch buffer. note: the same code is executed from flash and from ram memory. firmware description for low-power modes measurements the code starts with the mcu configuration (gpio, pcg, flash mode, and regulator used during the low-power mode). the low-power mode entering instruction is then executed and the microcontroller switches to the corresponding low-power mode. the measurement is taken when the mcu is actually in low-power mode. for more details about firmware configurations please refer to the zip file which contains the source codes related to this application note. stm8 oscin ai15049 oscin 5 v or 3.3 v t 0 v
AN2857 power consumption and wakeup time measurements and results doc id 15241 rev 3 21/31 5.1.2 power consumption results in run mode note: the results given above are different from those in the datasheets because a different reference code is used. the reference code us ed for flash and ram execution is the same. table 5. power consumption results in run mode, code executed from flash symbol parameter condition v dd = 3.3 v v dd = 5 v unit i tot supply current in run mode hse crystal f cpu = f master = 24 mhz 11.0 11.4 ma hse external clock f cpu = f master = 24 mhz 10.8 10.8 hse crystal f cpu = f master = 16 mhz 8.4 9.0 hse external clock f cpu = f master = 16 mhz 8.2 8.2 hsi f cpu = f master = 16 mhz 8.1 8.1 hsi f cpu = f master /128 = 125 khz 1.1 1.1 lsi f cpu = f master = 128 khz 0.55 0.55 table 6. power consumption results in run mode, code executed from ram symbol parameter condition v dd = 3.3 v v dd = 5 v unit i tot supply current in run mode hse crystal f cpu = f master = 24 mhz 5.2 5.6 ma hse external clock f cpu = f master = 24 mhz 5.0 5.0 hse crystal f cpu = f master = 16 mhz 3.7 4.1 hse external clock f cpu = f master = 16 mhz 3.5 3.5 hsi f cpu = f master = 16 mhz 3.4 3.4 hsi f cpu = f master /128 = 125 khz 1.0 1.0 lsi f cpu = f master = 128 khz 0.47 0.47
power consumption and wakeup time measurements and results AN2857 22/31 doc id 15241 rev 3 observations power consumption increases with clock frequency (f master ). when the code is executed from ram, the code execution time is longer than when the code is executed from flash. consumption does not depend on the supply voltage when an internal clock is used (hsi or lsi). this is because the internal oscillators are supplied by the internal 1.8 v. the effect of memory placement is not shown in ta b l e 5 and ta bl e 6 . however, if the size of a loop is smaller than the size of a memory block, placing the loop in the same memory block can reduce power consumption. in this case, only one block of memory is active. the effect of the instruction executed is not shown in ta bl e 5 and ta b l e 6 . however, consumption in run mode depends on the exec uted instruction and the operands of this instruction. examples of instructions which do not consume at a high rate include: inc a and nop. examples of instructions which consume at a high rate include ld (from flash) and add a, #$01. consumption of the cryst al oscillator is about: ? 5 v: 0.6 ma ? 3.3 v: 0.3 ma 5.1.3 power consumption results in wait mode observations: power consumption increases with clock frequency (f fmaster ). consumption does not depend on the supply voltage when an internal clock is used (hsi or lsi). this is because the internal oscillators are supplied by the internal 1.8 v. consumption of the cryst al oscillator is about: ? 5 v: 0.6 ma ? 3.3 v: 0.3 ma table 7. power consumption results in wait mode symbol parameter condition v dd = 3.3 v v dd = 5 v unit i tot supply current in wait mode hse crystal f cpu = f master = 24 mhz 2.0 2.4 ma hse external clock f cpu = f master = 24 mhz 1.8 1.8 hse crystal f cpu = f master = 16 mhz 1.6 2.0 hse external clock f cpu = f master = 16 mhz 1.4 1.4 hsi f cpu = f master = 16 mhz 1.2 1.2 hsi f cpu = f master /128 = 125 khz 1.0 1.0 lsi f cpu = f master = 128 khz 0.50 0.50
AN2857 power consumption and wakeup time measurements and results doc id 15241 rev 3 23/31 5.1.4 power consumption resul ts in active halt mode these measurements are taken when the device is in halt phase of active halt mode. 5.1.5 power consumption results in halt mode table 8. power consumption results in active halt mode (mvr on lpvr off) symbol parameter condition v dd = 3.3 v v dd = 5 v unit clock flash i tot supply current in active halt mode (halt phase) hse crystal 24 mhz f awu = 24 mhz/prsc = 128 khz on 700 1260 a off 640 1200 hse crystal 16mhz f awu = 16 mhz/prsc = 128 khz on 600 1000 off 540 940 hse crystal 8 mhz f awu = 8 mhz/prsc = 128 khz on 500 1040 off 440 980 hse crystal 4 mhz f awu = 4 mhz/prsc = 128 khz on 460 970 off 400 910 lsi 128 khz f awu = 128 khz on 200 200 off 140 140 table 9. power consumption results in active halt mode (mvr off lpvr on) symbol parameter condition v dd = 3.3 v v dd = 5 v unit clock flash i tot supply current in active halt mode (halt phase) lsi 128 khz f awu = 128 khz on 66 68 a off 9 11 table 10. power consumption results in halt mode (mvr off lpvr on) symbol parameter condition v dd = 3.3 v v dd = 5 v unit i tot supply current in halt mode flash in operating mode 61.5 63.5 a flash in power-down mode 4.5 6.5
power consumption and wakeup time measurements and results AN2857 24/31 doc id 15241 rev 3 5.1.6 conclusions power consumption depends on: supply voltage clock frequency the results presented in this section, show that the functioning mode (run, wait, active halt and halt) of the mcu impacts consumption and can greatly reduce it. for active halt and halt mode, the user can choose which regulator to be used (mvr or lpvr) and the flash state (operating mode or power-down mode). using the results presented in section 5.1: power consumption measurements and results , consumption is estimated as follows: mvr: about 135 a flash: about 60 a awu + lsi: about 4 a 5.2 wakeup time measurements and results wakeup time measurements are taken in low-power modes. results are given in ta bl e 1 1 to ta bl e 1 4 . the wake-up time is measured from the interrupt event to the first instruction execution in the interrupt routine. figure 7 explains the wakeup time measurement. note: in the stm8s and stm8a datasheets the wake-up time is not defined in the same way. it does not include the fetch of the interrupt vector. 5.2.1 measurement configuration hardware environment the following hardware configuration is used to measure the mcu wakeup time: one pin of the microcontroller is used as an interrupt input pin. another pin is used as an output pin. the cpu clock is outputted on the clk_cco pin. these three pins are monitored on an oscilloscope. firmware description the code starts with the mcu configuration. one pin (pb5) is configured as an input interrupt. after configuration, the mcu switches into low-power mode. when an external interrupt is triggered, the mcu wakes up, and executes the interrupt routine. the interrupt routine causes a pin (pb1) to toggle. note: the results given in this section take into account the interrupt latency times because they include the time between the external event occurring and the first instruction of the interrupt routine being executed. the code executed in the interrupt routine is described below: ld a,#$02 ld $5005,a ld a,#$00 ld $5005,a
AN2857 power consumption and wakeup time measurements and results doc id 15241 rev 3 25/31 figure 7. wakeup time measurement diagram 5.2.2 wakeup time results in most of cases, power supply voltage has no effect on wakeup time. the minus sign (-) in ta bl e 1 1 to ta b l e 1 4 below indicates that the wakeup time is the same for both power supply voltages. 5.2.3 wakeup time results in wait mode the wakeup time from wait mode is not alwa ys the same because the wakeup event is synchronized with the cpu clock. the variation range is about one period of the cpu clock. data given in ta b l e 1 1 are maximum values. external event output pin f cpu t wku execution of ld a, #$02 ai15050 table 11. wakeup time results in wait mode symbol parameter condition v dd = 3.3 v (1) 1. the minus sign (-) indicates that the wakeup time is the same as for v dd = 5 v. v dd = 5 v unit t wu(wfi) wakeup time from wait mode hse crystal f cpu = f master = 24 mhz -1.0 s hse crystal f cpu = f master = 16 mhz -0.75 hse crystal f cpu = f master = 8 mhz -1.4 hse crystal f cpu = f master = 4 mhz -2.7 hsi f cpu = f master = 16 mhz -0.75 hsi f cpu = f master /128 = 125 khz -80 lsi f cpu = f master = 128 khz -94
power consumption and wakeup time measurements and results AN2857 26/31 doc id 15241 rev 3 observations when no wait state is added, wakeup time from wait mode is linked only to the f master and to the f cpu clock frequencies. wakeup time from wait mode can be calculated using equation 3 and equation 4 . equation 3 equation 4 the wakeup time at 24 mhz is longer than at 16 mhz. this is because the wait state has to be introduced for accessing the flash memory. 5.2.4 wakeup time results in active halt mode for active halt mode measurements, the awu clock is always lsi. in ta b l e 1 2 and ta b l e 1 3 below, the clock in the ?conditio n/clock? column is the clock used before entering active halt mode. the wakeup time from active halt mode is not always the same due to a sampling effect, similar to that for wait mode. the variation range is about one period of the awu clock (7.8125 s). data given in ta bl e 1 2 and ta b l e 1 3 are maximum values which include sampling of the awu clock cycle. t wu wfi () min 21f master ? () 91f cpu ? () + = t wu wfi () max 21f master ? () 101f cpu ? () + = table 12. wakeup time results in active halt mode (mvr) symbol parameter condition v dd = 3.3 v (1) 1. the minus sign (-) indicates that the wakeup time is the same for v dd = 5 v. v dd = 5 v unit clock others t wu(ah) wakeup time from active halt mode hsi (16 mhz) flash on - 9 s flash off - 11 hse (16 mhz crystal) fast clk wakeup on flash off -11 fast clk wakeup off flash off 394 543 hse (4 mhz crystal) fast clk wakeup on flash off -11 fast clk wakeup off flash off 1627 1274
AN2857 power consumption and wakeup time measurements and results doc id 15241 rev 3 27/31 observations when fast clock wakeup is enabled, wakeup time always equals hsi wakeup time because the mcu automatically wakes up on hsi. when the wakeup clock is the hse crystal, wakeup time is very long and depends on the supply voltage and the cr ystal used. this is due to the stabilization time of the oscillator. this long wakeup time can be avoided by: ? using the fast clock wakeup feature. ? programing a shorter stabilization time in the hsecnt option byte (refer to the option bytes section of the stm8s and stm8a datasheets). by default, a delay of 2048 oscillator cycles is inserted before th e clock signal is released (the default value of 2048 oscillator cycles is used in the above measurements). data for ?hse crystal/flash on? are not given in ta bl e 1 2 because the wakeup time of the flash is always the same. the wakeup time of the flash is about 2 s. the wakeup time of the mvr is about 50 s. 5.2.5 wakeup time results in halt mode observations the wakeup time of the flash is about 2 s (the same as for active halt mode). the wakeup time in halt mode (lpvr) is shorter than in active halt mode (see ta bl e 1 2 ). note that the data in ta b l e 1 2 include one awu clock cycle sampling delay. table 13. wakeup time results in active halt mode (lpvr) symbol parameter condition v dd = 3.3 v (1) 1. the minus sign (-) indicates that the wakeup time is the same for v dd = 5 v. v dd = 5 v unit clock others t wu(ah) wakeup time from active halt mode hsi (16 mhz) flash on - 56 s flash off - 58 table 14. wakeup time results in halt mode (lpvr) symbol parameter condition v dd = 3.3 v v dd = 5 v unit clock others t wu(h) wakeup time from halt mode hsi (16 mhz) flash on - 52 s flash off - 54
power consumption and wakeup time measurements and results AN2857 28/31 doc id 15241 rev 3 5.2.6 conclusions the global wakeup time of the device c an be viewed as the sum of the following: wakeup time of the main voltage regulator (if it is switched off during the low-power mode). stabilization time of the oscillator (if it is switched off during the low-power mode). wakeup time of the flash memory (if it is switched off during the low-power mode). interrupt latency for the wake up event trigger.
AN2857 power management tips doc id 15241 rev 3 29/31 6 power management tips 6.1 rules to help minimize power consumption switch off all unused peripherals (peripherals are switched off by default except the usart, linuart and swim) and use the pcg feature (through the clk_pckenrx registers) to disable the clock provided to t he unused peripherals (the clock is provided by default). refer to section 3.2: clock configuration and power management for more details. in run mode, if the size of a loop is smaller than the size of a block, the loop code must be located in one block. all unused port pins should be configured as output low level. do not leave any unused i/o pin configured as a floating input wh ich could lead to useless high consumption. use wait mode if you need external interrupt capability in low-powe r mode and if some peripherals have to remain active. use the appropriate v dd value because the higher the v dd value, the more power is consumed. use the minimum possible frequency for your application. the eight cpu prescalers and four hsi prescalers allow the required frequency value to be fitted to the application. 6.2 choosing the optimal low-po wer mode for an application application powered by a battery where the mcu is in sleep mode most of the time: ? if the mcu is woken up due to external events, no time tracking is necessary and power consumption has to be as low as possible. in this case, halt mode is advised to extend battery life as much as possible. ? active halt mode with awu is advised if the application does not depend on external events but needs a non accurate periodic wakeup. application powered by a battery where the mcu is awake most of the time: ? active halt mode is advised if the mcu has to perform a few periodic actions during which no peripheral has to stay on. ? wait mode is advised if at least one peripheral has to stay on all the time and an interrupt can wake up the mcu. application supplied by mains but where consumption is critical: ? run mode, with a clock prescaler adapted to the application requirement, is advised if the mcu has to run all the time.
revision history AN2857 30/31 doc id 15241 rev 3 7 revision history table 15. revision history date revision description of changes 09-jan-2009 1 initial release 08-jul-2009 2 updated table 3 on page 12 updated figure 7 on page 25 25-aug-2011 3 updated to refer to both stm8s and stm8a products
AN2857 doc id 15241 rev 3 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of AN2857

	To Download AN2857 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .